1. Field of the Invention
The present invention relates to an interconnection structure for use in electronic devices including integrated semiconductor circuits such as a VLSI circuit, a ULSI circuit, or the like, and a method of manufacturing such an interconnection structure.
2. Description of the Related Art
To meet requirements for smaller sizes and higher packing densities, electronic devices including integrated semiconductor circuits such as a VLSI circuit, a ULSI circuit, or the like incorporate a multilayer interconnection structure including interconnections and electrodes (hereinafter collectively referred to as "interconnections") with interlayer insulating layers disposed therebetween. Efforts are being made to increase the density of and reduce the pattern of interconnections in electronic devices to meet demands for electronic devices of much smaller sizes and higher packing densities.
Interconnections on an upper surface of interlayer insulating layer are connected, by way of ohmic contact, through connecting holes such as contact holes or via holes defined in the interlayer insulating layer to other interconnections or semiconductor regions (hereinafter referred to as "contact regions") such as impurity-diffused regions of Si semiconductors beneath the interlayer insulating layer. The connecting holes are also required to be smaller in diameter.
It is necessary that the interlayer insulating layers have a certain thickness in order to provide a desired level of electric reliability and avoid the problem of parasitic capacitance. Consequently, the aspect ratio (depth/diameter) of the connecting holes is relatively large.
If a metallic interconnection layer containing Al, e.g., Al--Si with 1% of Si or Al--Si--Cu, is connected, by way of ohmic contact, to a contact region through a connecting hole having a relatively large aspect ratio, then a barrier metal layer is employed as a base layer for the metallic interconnection layer.
One conventional structure having a metallic interconnection layer containing Al which is connected to a contact region through ohmic contact through a connecting hole is illustrated in FIG. 1 of the accompanying drawings.
As shown in FIG. 1, an interconnection or conducting path is connected to a contact region which comprises a semiconductor region 2 of an Si semiconductor substrate 1 through a connecting hole 4 defined in an interlayer insulating layer 3 deposited on the Si semiconductor substrate 1. More specifically, a barrier metal layer is deposited on the interlayer insulating layer 3 including the connecting hole 4 by sputtering or the like. The barrier metal layer is composed of a Ti layer 5 which well adheres to Si, for example, of the semiconductor region 2, and a TiON layer 6 which prevents Al of the interconnection from spiking the Si semiconductor substrate 1. An interconnection or conducting path 7 containing Al is deposited on the barrier metal layer by sputtering or the like.
A thermally oxidized device-separating thick insulating layer 8, i.e., LOCOS, is formed on the Si semiconductor substrate 1. A channel-stop region 9 of a high impurity concentration is disposed on the Si semiconductor substrate 1 beneath the thick insulating layer 8.
With the arrangement shown in FIG. 1, however, the wettability of the interconnection layer 7 containing Al with the TiON layer 6 is poor. Therefore, as indicated at a in FIG. 1, a region which is not covered with the interconnection layer 7, i.e., with a coverage of 0% or nearly 0%, is produced, causing electrical and mechanical reliability problems.
One solution is to deposit a TiN layer 16 in place of the TiON layer 6 in the barrier metal layer to provide better wettability with the interconnection layer 7 containing Al. While the TiN layer 16 well adheres to the interconnection layer 7, i.e., its electrical and mechanical reliability is higher, the barrier capability of the TiN layer 16 is lower. Specifically, when the assembly is heated to 400.degree. C. to 500.degree. C. after the interconnection layer 7 has been deposited, it is necessary for the TiN layer 16 to have a large thickness of 115 nm, for example, in order to reliably prevent Al of the interconnection layer 7 from spiking the semiconductor region 2, for example, which is formed in the semiconductor substrate 1 by mutual diffusion of Si therefrom. Therefore, even if the connecting hole 4 has a reduced effective diameter, the connecting hole 4 may not be covered well with the interconnection layer 7 particularly when the aspect ratio of the connecting hole 4 is large.